(1) Field of the Invention
The present invention relates to manufacturing of semiconductor devices in general, and in particular, to manufacturing of contact holes using self-aligned etching and tapering processes together.
(2) Description of the Related Art
Conventional fabrication of contact holes in semiconductor devices normally requires several masking and etching process steps. Holes, or windows, that are made to open up on to areas where there are semiconductor devices that are formed in a substrate, such as silicon or gallium-arsenide, are called contact holes. On the other hand, holes that are made to form a connection between conductive layers in a semiconductor wafer are known as via holes. Whether contact or via holes, they are later filled with conductive material to establish contact between the various components of an integrated circuit.
Holes are made by etching through the insulation layers that separate the conductive layers. Specifically, a photoresist is first applied as a thin film to the insulating layer and subsequently exposed through a mask. The mask contains clear and an opaque features that define the pattern of a hole. The area of the photoresist film which is exposed to light is soluble (in the case of a positive photoresist) and the exposed portion is removed in a subsequent development process. The remainder of the photoresist film acts as an etch-mask. A succeeding etching step removes the exposed part of the insulating layer but does not remove the insulating layer located under the photoresist mask. This results in the formation of a hole.
In fabricating holes in the sub-micron range, aligning hole patterns on a mask over the area where the hole is to be formed can be critical. As is well known, in a MOS structure for example, the area of the source/drain regions cannot easily be minimized commensurate with the sub-micron technologies because the contact hole has to be aligned to these regions with a separate masking step, and extra area has to be allocated for misalignment. However, the larger area results in increased source/drain-to-substrate junction capacitance, which slows down the device speed. Also, if the contact resistance is to be minimized for smaller contact holes contacting sub-micron size devices, all of the area that is available must be used without sacrificing any areas for want of proper alignment. Therefore, alternative contact structures must be devised. One such structure is that which is formed by means of what is called self-alignment. In a self-aligned contact (SAC) structure, the contact on the source/drain regions is formed at the same time that another contact is formed on the gate of a MOS structure, hence eliminating the need for separate masking steps for forming contact with the gate and then the source/drain. After the formation of contacts, additional steps are needed to form the contact holes to make the necessary connections between the devices of the integrated circuit, as is well known in the art. Furthermore, depending upon whether they are peripheral circuits or cells in the integrated circuit chip, different steps may be required in making the holes because of different etch requirements for different underlying materials in the holes, as will be described later along with a hole contouring method for tapering.
A SAC process for forming contact with silicon is the well-known self-aligned silicide (salicide) process which reduces the number of masking steps. Silicides are binary metal compounds of silicon which are formed by well known methods such as co-evaporation or co-sputtering of a refractory metal and silicon. It is the reaction of suicides with silicon that enables the SAC process. Namely, after the source and drain regions (n.sup.+) of the well-known MOS structure (see, for example, S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 3, Lattice Press, Sunset Beach, Calif., 1990, p 398) on a substrate (10) shown in FIG. 1a have been implanted to form the source/drain junctions, the polysilicon (poly-Si) gate (30) sidewall spacers (40) are formed. As is commonly practiced in the art, sidewall spacers are formed by first depositing oxide on the MOS structure and etching anisotropically to leave the corners of the gate filled with residual oxide to form the spacers (40) shown in FIG. 1b. Oxide spacers prevent the gate and source/drain areas from being electrically connected when a metal (50) used to form silicide is deposited. As the whole structure is then heated, the deposited metal reacts with silicon wherever it contacts with silicon including polysilicon. Everywhere else, the metal remains unreacted. The unreacted metal is selectively removed through the use of an etchant that does not attack the silicide (60), the silicon substrate (10), or oxide (20). As a result, each exposed source and drain region is now completely covered by a silicide film and none elsewhere as shown in FIG. 1c.
Following prior art, the next step in completing the process of forming a contact is to deposit an insulating dielectric (70) onto the silicide, and open holes (90) through it down to the silicide layer. Finally, a metal (95) is deposited into the contact holes to make contact with the silicide, thus forming an integrated circuit. It will be noted that after the formation of silicon contact by means of self-aligned salicide, additional masking and etching steps are required to form the contact holes. Furthermore, it. will be seen below that the contact holes must also be shaped or contoured in a manner that makes them reliable for which additional steps are required. A method is proposed in this invention where not only self-aligned contacts (SAC) but also self-aligned holes (SAH) can be formed together with the process of contouring the walls of the hole. Thus, at the same time the masking steps are reduced, contact reliability as well as planarization, as explained later, are improved.
As is well appreciated in the art, the geometry and size of the holes govern how well and reliably the contacts can be made. For example, if the walls of the hole are straight and vertical, then the metal that is deposited into the hole may not cover the edge of the hole properly. That is, the metal at the edge of the hole may be sharp and thin, giving rise to higher electrical resistance, or, for that matter, to breakage later on. In prior art, this is sometimes referred to as the "step coverage" problem and numerous methods have been devised to overcome it. Contouring the sidewalls or tapering the edge of the hole are some of the techniques that are used and are described below briefly. However, it will be seen that the conventional techniques are complex and complicated.
The additional steps in forming contact holes (90) over source/drain regions after the formation of SAC are shown in FIGS. 2a-2c. FIG. 2a depicts the regions near either the source or drain of FIG. 1e. In order to form contact hole (90), substrate (10) is first covered with an oxide which typically is thermal oxide (70). (It will be noted that like elements are denoted by like reference numerals through the various Figures). Then, photoresist (80) is applied as a thin film over the oxide layer (70). It is now necessary to image the photoresist with the contact hole pattern using the well-known photolithographic techniques including the development step as explained earlier. The remaining photoresist film is then used as an etch-mask (80) containing openings (85) for contact holes to be formed in the next step. A "window" or contact hole is etched into oxide layer (70) through hole pattern (85) in photoresist mask (80). After the formation of contact hole (90), photoresist mask (80) is removed as shown in FIG. 2b.
Prior to the final step of deposition of metal (95), the surface of the silicon wafer is cleaned to remove the thin native-oxide layer that rapidly forms on a silicon surface whenever it is exposed to oxygen, such as in air. Metal film (90) is deposited onto the wafer surface to make contact with the silicon wherever contact holes have been formed in the oxide. In the simplest contact structure, the deposited metal is aluminum (Al) or an Al:Si alloy. For completeness, we note that after deposition, the contact structure is subjected to a thermal cycle known as sintering of annealing. The purpose of this step is to bring the metal and silicon surfaces into intimate contact. The nature and the area of the contact become important for small contact holes required with especially, submicron technologies.
Various methods are used for formation of contact hole windows. For relatively large openings greater than about 2.0 micrometers (.mu.m), wet etching is often used. Its widespread use stems from the fact that the liquid etchant systems can be formulated to have very high selectivity to both the substrate and masking layers. That is, during the etching of contact holes in the oxide, neither the mask which is usually a photoresist- nor the substrate materials are very much affected. The isotropic nature of wet etching, however, makes it difficult when etching smaller sized and closely patterned contact holes, especially for the sub-micron VLSI and ULSI (ultra large scale integrated) technologies. This is because, when etching progresses at the same rate in all directions, that is, isotropically, undercutting occurs if the thickness of the film layer that is being etched is comparable to the minimum pattern dimensions. Of course, undercutting between small and closely spaced holes would be intolerable. Hence, since many films used in VLSI fabrication are 0.5-1.0 .mu.m thick, reproducible and controllable transfer of patterns in the 1-2 .mu.m range becomes difficult if not impossible with wet etching, according to S. Wolf in his book "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif., 1990, p. 539. As is well known, an alternative to "wet" etching is the "dry" etching which offers the capability of anisotropic removal of material. Dry etching essentially consists of "ion assisted etching processes" of which reactive ion etching (RIE) providing anisotropic etching, and plasma etching providing isotropic etching are well known.
Though anisotropic etching is useful because it avoids undercutting, that is not always desirable for the reasons indicated in FIG. 2b. When the sidewalls of hole (90) are formed vertically as shown in FIG. 2b by dry etching, the step edge (73) of the hole is not usually well covered when the hole is later filled with metal (95). Poor step coverage can lead to electrical discontinuities. This problem can sometimes be alleviated by first using wet or dry isotropic etching at the mouth of the opening (85) in FIG. 2a, and then following it with anisotropic etching so that the resulting hole geometry is contoured rather than being straight and vertical.
Contouring holes come into play in a different way when forming holes having different depths in an insulating layer which covers a semiconductor substrate. Via holes, for example, connecting different conductive layers reach to different depths in a wafer. In order to keep the misalignment to a minimum between holes having different depths, U.S. Pat. No. 5,444,020 teaches a method of selectively etching the upper parts of the insulating layer which correspond to contact holes having a greater depth the shallowest contact hole, using a first mask pattern. This first etch is accomplished by means of isotropic etching to form large contoured hole in the upper parts of the layer. Then a second etch step is used to selectively etch the remainder of the insulating layer for all of the contact holes at the same time using a second mask pattern. The second etch is anisotropic to yield vertical straight walls.
It is evident that conventional methods of forming holes--irrespective of whether they are contact holes or via holes--involves plurality of masking and etching steps. Although self-aligned contact (SAC) techniques are utilized for forming contacts, thus eliminating one masking step, additional masking and etching steps are still needed for forming contact holes. It will be apparent to those skilled in the art that a method for eliminating the additional steps is needed. It is disclosed in this invention that by integration of a novel self-aligned hole (SAH) etching process with taper contouring, the number of steps can be reduced and, at the same time, the reliability of the contact improved.